Towards Reliable Benchmarks of Timed Automata

The verification of the time-dependent behavior of safety-critical systems is important, as design problems often arise from complex timing conditions. One of the most common formalisms for modeling timed systems is the timed automaton, which introduces clock variables to represent the elapse of time. Various tools and algorithms have been developed for the verification of timed automata. However, it is hard to decide which one to use for a given problem as no exhaustive benchmark of their effectiveness and efficiency can be found in the literature. Moreover, there does not exist a public set of models that can be used as an appropriate benchmark suite. In our work we have collected publicly available timed automaton models and industrial case studies and we used them to compare the efficiency of the algorithms implemented in the Theta model checker. In this paper, we present our preliminary benchmark suite, and demonstrate the results of the performed measurements

Modular analysis of gene expression data with R

Summary: Large sets of data, such as expression profiles from many samples, require analytic tools to reduce their complexity. The Iterative Signature Algorithm (ISA) is a biclustering algorithm. It was designed to decompose a large set of data into so-called ‘modules'. In the context of gene expression data, these modules consist of subsets of genes that exhibit a coherent expression profile only over a subset of microarray experiments. Genes and arrays may be attributed to multiple modules and the level of required coherence can be varied resulting in different ‘resolutions' of the modular mapping. In this short note, we introduce two BioConductor software packages written in GNU R: The isa2 package includes an optimized implementation of the ISA and the eisa package provides a convenient interface to run the ISA, visualize its output and put the biclusters into biological context. Potential users of these packages are all R and BioConductor users dealing with tabular (e.g. gene expression) data. Availability: http://www.unil.ch/cbg/ISA Contact: [email protected]

Parallelization of Graph Transformation Based on Incremental Pattern Matching

oai:journal.ub.tu-berlin.de:article/265Graph transformation based on incremental pattern matching explicitly stores all occurrences of patterns (left-hand side of rules) and updates this result cache upon model changes. This allows instantaneous pattern queries at the expense of costlier model manipulation and higher memory consumption. Up to now, this incremental approach has considered only sequential execution despite the inherently distributed structure of the underlying match caching mechanism. The paper explores various possibilities of parallelizing graph transformation to harness the power of modern multi-core, multi-processor computing environments: (i) incremental pattern matching enables the concurrent execution of model manipulation and pattern matching; moreover, (ii) pattern matching itself can be parallelized along caches

Adaptive Step Size Control for Hybrid CT Simulation without Rollback

The Hybrid CT approach for simulating cyber-physical systems uses continuous time simulation and provides wrappers for discrete event components that implement the required interfaces. Besides the general obstacles of continuous time simulation, Hybrid CT introduces new challenges, such as creating wrappers, detecting discrete events (with minimal latency), and finding the correct balance between the simulation step sizes required by different components. We propose an adaptive step size controller that uses high level information of the model and the simulation (e.g. types of components, critical values of variables) to adjust the step size based on the possibility of the detection of a discrete event in the following step. Besides overcoming the challenges of Hybrid CT simulation the component also improves threshold-crossing detection. The proposed approach does not require step rejection (rollback), that discrete event components often fail to support. In this paper we present the step size controller, demonstrate its usability on industrial case studies and evaluate the component both theoretically and based on measurements performed on our implementation that was integrated to the OMSimulator. We show that adaptive step size control can be used to bridge the gap between continuous time and discrete event simulation

Incrementalizing Lattice-Based Program Analyses in Datalog

Program analyses detect errors in code, but when code changes frequently as in an IDE, repeated re-analysis from-scratch is unnecessary: It leads to poor performance unless we give up on precision and recall. Incremental program analysis promises to deliver fast feedback without giving up on precision or recall by deriving a new analysis result from the previous one. However, Datalog and other existing frameworks for incremental program analysis are limited in expressive power: They only support the powerset lattice as representation of analysis results, whereas many practically relevant analyses require custom lattices and aggregation over lattice values. To this end, we present a novel algorithm called DRedL that supports incremental maintenance of recursive lattice-value aggregation in Datalog. The key insight of DRedL is to dynamically recognize increasing replacements of old lattice values by new ones, which allows us to avoid the expensive deletion of the old value. We integrate DRedL into the analysis framework IncA and use IncA to realize incremental implementations of strong-update points-to analysis and string analysis for Java. As our performance evaluation demonstrates, both analyses react to code changes within milliseconds